Research on controlling L2 cache size on AD102 GPU
After my previous post about adding 64G BAR1 support on 4090 48G card, dolphin made an EFI program to unlock the card, so that it can work with Windows. Some friend posted an AI generated video on Bilibili and it has received nearly 60k views, and 1k likes so far (as of night, 10/28/2026).
One of the comments asked whether the L2 cache can be enlarged. Given that the FP16 command issue rate can be overridden, I thought the L2 cache might be, too. So I asked Codex to run some experiments.
TL, DR: Codex couldn’t unlock 96 MiB of L2. In the tests, the software mask added disabled slices but did not clear existing disable bits. The mask survived a PCIe function-level reset (FLR), but with every slice masked, GPU firmware (GFW) did not complete booting afterward. No changed cache capacity was measured with CUDA.